The present invention relates to processing engines of intermediate stations in a computer network and, in particular, to the architecture of a processing element of a programmable processing engine.
Computer architecture generally defines the functional operation, including the flow of information and control, among individual hardware units of a computer. One such hardware unit is the processor or processing engine which contains arithmetic and logic processing circuits organized as a set of data paths. In some implementations, the data path circuits may be configured as a central processing unit (CPU) whose operations are defined by a set of instructions. The instructions are typically stored in a control (instruction) memory and specify a set of hardware functions that are available on the CPU.
Specifically, the fields of an instruction specify commands which supply signals for conditioning and clocking the data paths. If the structure of the instruction allows only the specification of a single command at a time, the instruction is a vertical instruction. Only the necessary commands are specified in this type of instruction, resulting in smaller control memory requirements; yet, it is not possible to take advantage of all possible parallelisms offered by the hardware, since only one command is executed at a time. A horizontal instruction specifies all possible commands which permits programmers to take full advantage of all parallelisms in a processor to build high-performance computers.
A high-performance computer may be realized by using a number of identical CPUs or processors to perform certain tasks in parallel. For a purely parallel multiprocessor architecture, each processor may have shared or private access to non-transient data, such as program instructions (e.g., algorithms) stored in a memory coupled to the processor. Access to an external memory is generally inefficient because the execution capability of each processor is substantially faster than its external interface capability; as a result, the processor often idles while waiting for the accessed data Moreover, scheduling of external accesses to a shared memory is cumbersome because the processors may be executing different portions of the program. On the other hand, providing each processor with private access to the entire program results in inefficient use of its internal instruction memory.
In an alternative implementation, the data paths may be configured as a pipeline having a plurality of processor stages. This configuration conserves internal memory space since each processor executes only a small portion of the program algorithm. A drawback, however, is the difficulty in apportioning the algorithm into many different stages of equivalent duration. Another drawback of the typical pipeline is the overhead incurred in transferring transient xe2x80x9ccontextxe2x80x9d data from one processor to the next in a high-bandwidth application.
One example of such a high-bandwidth application involves the area of data communications and, in particular, the use of a parallel, multiprocessor architecture as the processing engine for an intermediate network station. The intermediate station interconnects communication links and subnetworks of a computer network to enable the exchange of data between two or more software entities executing on hardware platforms, such as end stations. The stations typically communicate by exchanging discrete packets or frames of data according to predefined protocols, such as the Transmission Control Protocol/Internet Protocol (TCP/IP), the Internet Packet Exchange (IPX) protocol, the AppleTalk protocol or the DECNet protocol. In this context, a protocol consists of a set of rules defining how the stations interact with each other.
A router is an intermediate station that implements network services such as route processing, path determination and path switching functions. The route processing function determines the type of routing needed for a packet, whereas the path switching function allows a router to accept a frame on one interface and forward it on a second interface. The path determination, or forwarding decision, function selects the most appropriate interface for forwarding the frame. A switch is also an intermediate station that provides the basic functions of a bridge including filtering of data traffic by medium access control (MAC) address, xe2x80x9clearningxe2x80x9d of a MAC address based upon a source MAC address of a frame and forwarding of the frame based upon a destination MAC address. Modem switches further provide the path switching and forwarding decision capabilities of a router. Each station includes high-speed media interfaces for a wide range of communication links and subnetworks.
The hardware and software components of these stations generally comprise a communications network and their interconnections are defined by an underlying architecture. Modern communications network architectures are typically organized as a series of hardware and software levels or xe2x80x9clayersxe2x80x9d within each station. These layers interact to format data for transfer between, e.g., a source station and a destination station communicating over the internetwork. Predetermined services are performed on the data as it passes through each layer and the layers communicate with each other by means of the predefined protocols. Examples of communications architectures include the IPX communications architecture and, as described below, the Internet communications architecture.
The Internet architecture is represented by four layers which are termed, in ascending interfacing order, the network interface, internetwork, transport and application layers. These layers are arranged to form a protocol stack in each communicating station of the network. The lower layers of the stack provide internetworking services and the upper layers collectively provide common network application services. For example, the network interface layer comprises physical and data link sublayers that define a flexible network architecture oriented to the implementation of local area networks (LANs). Specifically, the physical layer is concerned with the actual transmission of signals across the communication medium and defines the types of cabling, plugs and connectors used in connection with the medium. The data link layer (xe2x80x9clayer 2xe2x80x9d) is responsible for transmission of data from one station to another and may be further divided into two sublayers: logical link control (LLC) and MAC sublayers.
The MAC sublayer is primarily concerned with controlling access to the transmission medium in an orderly manner and, to that end, defines procedures by which the stations must abide in order to share the medium. In order for multiple stations to share the same medium and still uniquely identify each other, the MAC sublayer defines a hardware or data link MAC address. This MAC address is unique for each station interfacing to a LAN. The LLC sublayer manages communications between devices over a single link of the internetwork.
The primary network layer protocol of the Internet architecture is the Internet protocol (1P) contained within the internetwork layer (xe2x80x9clayer 3xe2x80x9d). IP is a network protocol that provides internetwork routing and relies on transport protocols for end-to-end reliability. An example of such a transport protocol is the Transmission Control Protocol (TCP) contained within the transport layer. The term TCP/IP is commonly used to refer to the Internet architecture. Protocol stacks and the TCP/IP reference model are well-known known and are, for example, described in Computer Networks by Andrew S. Tanenbaum, printed by Prentice Hall PTR, Upper Saddle River, N.J., 1996.
Data transmission over the network therefore consists of generating data in, e.g., a sending process executing on the source station, passing that data to the application layer and down through the layers of the protocol stack where the data are sequentially formatted as a frame for delivery over the medium as bits. Those frame bits are then transmitted over the medium to a protocol stack of the destination station where they are passed up that stack to a receiving process. Although actual data transmission occurs vertically through the stacks, each layer is programmed as though such transmission were horizontal. That is, each layer in the source station is programmed to transmit data to its corresponding layer in the destination station. To achieve this effect, each layer of the protocol stack in the source station typically adds information (in the form of a header) to the data generated by the sending process as the data descends the stack.
For example, the internetwork layer encapsulates data presented to it by the transport layer within a packet having a network layer header. The network layer header contains, among other information, source and destination network addresses needed to complete the data transfer. The data link layer, in turn, encapsulates the packet in a frame, such as a conventional Ethernet frame, that includes a data link layer header containing information, such as MAC addresses, required to complete the data link functions. At the destination station, these encapsulated headers are stripped off one-by-one as the frame propagates up the layers of the stack until it arrives at the receiving process.
Increases in the frame/packet transfer speed of an intermediate station are typically achieved through hardware enhancements for implementing well-defined algorithms, such as bridging, switching and routing algorithms associated with the predefined protocols. Hardware implementation of such an algorithm is typically faster than software because operations can execute in parallel more efficiently. In contrast, software implementation of the algorithm on a general-purpose processor generally performs the tasks sequentially because there is only one execution path. Parallel processing of conventional data communications algorithms is not easily implemented with such a processor, so hardware processing engines are typically developed and implemented in application specific integrated circuits (ASIC) to perform various tasks of an operation at the same time. These ASIC solutions, which are generally registers and combinational logic configured as sequential logic circuits or state machines, distinguish themselves by speed and the incorporation of additional requirements beyond those of the basic algorithm functions. However, the development process for such an engine is time consuming and expensive and, if the requirements change, inefficient since a typical solution to a changing requirement is to develop a new ASIC.
Thus, an object of the present invention is to provide a processor architecture for an intermediate station that approaches the speed of an ASIC solution but with the flexibility of a general-purpose processor.
Another object of the present invention is to provide a processing engine having a plurality of processing elements that efficiently execute conventional network service algorithms.
Still another object of the present invention is to provide an architecture of a processing element of a programmable processing engine that enables efficient and accurate context data transfers from one element to the next in a high-bandwidth application.
The invention comprises an architecture for efficiently passing data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient xe2x80x9ccontextxe2x80x9d data for processing by the CPU in accordance with instructions stored in the instruction memory. The memory manager manages interactions among the components of the processor complex by, inter alia, mapping a contiguous memory address space viewed by the CPU to the contents of the various memories residing within the processor complex.
In accordance with the invention, the architecture of the processor complex facilitates accurate passing of transient data among the stages of the engine. To that end, the processor complex further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. Data coherency is maintained by the memory manager constantly xe2x80x9csnoopingxe2x80x9d the data mover and CPU to determine the state of the data accessed by the data mover and CPU. A notable aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
Advantageously, the context passing technique described herein enhances the speed of data execution in a pipelined processing engine by substantially reducing the latency involved with passing the data among stages of the engine. The transient data entering the engine is dispatched to a processor complex stage of a pipeline for processing by a CPU prior to serially passing the data to a xe2x80x9cdownstreamxe2x80x9d processor complex stage. The processor complex architecture described herein facilitates the passing of transient data from an xe2x80x9cupstreamxe2x80x9d context memory to a corresponding downstream memory as the CPU processes the data. Thus, the invention transforms an otherwise serial data processing/passing procedure to a parallel process via pipelining.